1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to memory circuits.
2. Description of the Related Art
Memory circuits are used in a wide variety of electronic system devices, from large, powerful computers to small, handheld devices. Types of memory circuits include static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, and so on. Memory circuits may be implemented in various parts of a memory hierarchy, including as registers, as various levels of cache memories,
Many memory circuits require the use of a clock signal to synchronize read and write operations. Such memory circuits may employ dynamic logic on read and write port inputs that operate according to the received clock signal. Precharge operations may be incorporated for write and/or read operations as well. However, some memory circuits may be configured to allow for asynchronous read operations, utilizing static logic for decoding read addresses.
FIG. 1 illustrates a memory circuit configured to enable asynchronous reads of a memory. In FIG. 1, memory 1 includes multiple cells 7, logically arranged in one or more 16×128 grids (for the sake of simplicity, only portions of memory circuit are shown).
Write operations are synchronized to a clock signal (‘clk’) received by write address logic 3 and write data logic 4. During a write operation, a write address (e.g., wad[0:n−1]) is conveyed from write address logic 3 (and more particularly to flop circuits, e.g., latches or flip flops, one of which is shown here, labeled ‘SDC’, for the sake of example), synchronous with an edge of the clock signal, to write address decode logic 6. Data to be written, wd[0:m−1], is conveyed to write data logic 4 (and more particularly to flop circuits, e.g., latches or flip flops, one of which is shown here for the sake of example). The output of write address decode logic activates a write word line (‘WWL’) corresponding to the address received. Concurrent with this operation, the data to be written is conveyed from write data logic 4 synchronous with the clock edge. Two complementary write bit lines (‘wbl’ and ‘wbl—1’) are coupled to receive the data from write data logic 4 and convey the data to a selected cell 7. The data is written into the selected cell 7 and retained by that cell 7 after the clock has transitioned on its next edge.
In contrast to the write operations described above, read operations in memory 1 do not require any synchronization with a clock signal. Instead, once the address (e.g., rad[0:1], rad[n−1:2], etc.) is received by read address logic 2 (which is static logic in this example), it is conveyed to read address decode logic 5, which then decodes the address and asserts a signal on the read word line (‘rwl’) if the address indicates that the cell(s) 7 coupled to that word line are selected. The bits from the selected cell(s) 7 then propagate to corresponding local bit lines (‘lbl’), each of which includes a keeper 9 configured to hold the received logic value. Multiplexers 8 also receive select signals based on the received address. Thus, the bit received on the local bit lines from the selected cells propagate through the hierarchy of multiplexers 8, to a first global bit line (‘gbl0’), to a second global bit line (‘gbl1’), to a third global bit line (‘gbl2’), and finally to signal line ‘read_out’ (via buffer 10 in this example).